Many current integrated circuits are formed as multiple semiconductor chips on a common silicon wafer. After the basic process steps to form the circuits on the semiconductor chips are complete, the individual semiconductor chips are cut or singulated from the wafer. The singulated semiconductor chips are then usually mounted to structures, such as circuit boards, or packaged in some form of enclosure.
One frequently-used package consists of a substrate upon which a semiconductor chip is mounted. The upper surface of the substrate includes conductive pads. The semiconductor chip is manufactured with a plurality of bump pads. A collection of solder joints are provided between the bump pads of the semiconductor chip and the corresponding conductive pads of the package substrate to establish ohmic contact. After the semiconductor chip is seated on the substrate, a reflow process is performed to enable the solder bumps of the semiconductor chip to metallurgically link to the solder pads of the substrate.
For conventional semiconductor chip packages, there may be significant differences in the coefficients of thermal expansion (CTE) of the semiconductor chip, the package substrate and the solder joints. Large differences in CTE coupled with thermal stresses associated with testing and operation can impose significant strains on solder joints. To lessen the effects of differential CTE, an underfill material is often deposited between the semiconductor chip and the package substrate to act as a material that inhibits damage to the solder bumps due to mismatches in CTE.
One conventional type of substrate consists of a core laminated between upper and lower build-up layers. The core itself usually consists of four layers of glass-filled epoxy. The build-up layers, which may number four or more on opposite sides of the core, are formed from some type of resin. Various metallization structures are interspersed in the core and build-up layers in order to provide electrical pathways between pins or pads on the lowermost layer of the substrate and pads that bond with the chip solder bumps.
The core provides a particular stiffness to the substrate. Even with that provided stiffness, conventional substrates still tend to warp due to mismatches in the CTE's for the semiconductor chip, the underfill and the package substrate.
One conventional technique for addressing package substrate warpage involves the use of a stiffener ring on the semiconductor chip side of the package substrate. A typical conventional stiffener ring includes a central opening to accommodate the semiconductor chip while leaving a gap. The gap is used to dispense the aforementioned underfill. Underfill is conventionally dispensed in the gap as a dot or a line. After dispensing, capillary action draws the underfill into the space between the semiconductor chip and the package substrate.
Some conventional stiffener rings are made of metallic materials, while others are formed from plastics. Whether metal or plastic, an adhesive is typically used to secure the stiffener ring to the package substrate. The adhesive typically requires some form of thermal cure prior to chip attach to harden and bond the opposing surfaces. Prior to the thermal cure, the combination of the stiffener ring, the package substrate and the adhesive is placed in a fixture commonly referred to as a “bookcase.” The quality of the adhesive bond is dependent on precise alignment between the stiffener frame and the package substrate and a predictable bond line thickness. Conventional bookcases may not sufficiently restrain relative movements of the stiffener frame and the package substrate, and may not apply sufficiently uniform loading to achieve desired bond line thickness variations.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.